ISMM'04

Report on Memory Management Technical Program
at co-hosted OOPSLA and ISMM 2004,
October 23 - 28 October

Andy Cheadle

The 2004 International Symposium on Memory Management
October 24-25, 2004 Vancouver, British Columbia, Canada

Sponsored by ACM SIGPLAN

ISMM is a forum for research in management of dynamically allocated memory. Areas of interest include but are not limited to: explicit storage allocation and deallocation; garbage collection algorithms and implementations; compiler analyses to aid memory management; interactions with languages, operating systems, and hardware, especially the memory system; and empirical studies of allocation and referencing behaviour in programs that make significant use of dynamic memory.

Slides and links to the ACM Digital Library copies of the papers can be found at http://www.research.ibm.com/ismm04/.

Saturday, October 23, 2004

Two tutorial sessions were arranged for the day before the technical paper presentations:

Sunday, October 24, 2004

The ISMM keynote presentation was given by Steven Woo (Rambus, Inc.) on
DRAM and Memory System Trends.

Steven started by summarising the 'Processor-Memory Performance Gap' and the characteristics of a 'good' memory system, low latency, high bandwidth, high capacity and a high bank count (to limit thread contention). He highlighted the fact that DRAM latency is dramatically increasing from the CPU's point of view with the total memory system latency even higher. An emerging trend targeted at significantly reducing this latency is to integrate the memory controller with the CPU. The remainder of the talk discussed the issue of rising front side bus speeds fuelling the need for increased memory bandwidth. This can be achieved by widening the memory bus (64 -> 128 bit) or faster per-pin signalling. Steven focused on faster per-pin signalling and how the physical limitations are challenging the abilities of system designers to maintain good signal integrity and to deliver the bandwidth needed by these systems. At higher signalling speeds, signal integrity degrades due to interference caused by the reflection of earlier signals with subsequent signals as they meet at the 'tee' of each memory module. As a result the number of modules in the standard 'Multi-drop' or 'Stub-bus' arrangement that can be supported decreases. In turn, memory capacity in terms of number of DRAMs is shrinking. The need is for an increase in signal integrity and number of modules at the same time. The current solution to this problem is to use On-Die terminators that sit on top of each memory module not just at the end of the bus. Currently under development is a more scalable solution known as 'Advanced Memory Buffers', which daisy chain (without tees) to increase the number of modules while using differential point-to-point signalling to increase signalling integrity and enable higher speeds. Steven finished by touching on the challenges in shrinking system form factors and achieving reduced power consumption for mobile and handheld devices.

 

The following gives a brief description of each of the technical paper presentations, the slides for which can be found at: http://www.research.ibm.com/ismm04/

Session I: Concurrency

Session II: New Garbage Collection Algorithms and Strategies

Wild and Crazy Ideas

The 'Wild and Crazy Ideas' forum provided an arena for informal presentation of researcher's 'off the cuff' ideas. The following were presented:

Monday, October 24, 2004

Session III: Regions, Compiler Support

Session IV: Diverse Topics

Session V: Implementation Techniques

19th Annual ACM Conference on Object-Oriented Programming, Systems, Languages, and Applications October 24-28, 2004 Vancouver, British Columbia, Canada

Sponsored by ACM SIGPLAN

The OOPSLA technical paper sessions showcase research contributions and empirical results in object-oriented languages, systems, and applications. Twenty seven technical papers were presented in nine sessions and covered a range of topics including: novel software design techniques, advanced programming language features, analysis tools, run-time systems, and new approaches to validating and optimizing programs.

The following four papers, relating to memory management, were presented:

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